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tm 74abt573 octal d-type latch with 3-state outputs march 2007 ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 74abt573 octal d-type latch with 3-state outputs features inputs and outputs on opposite sides of package allow easy interface with microprocessors useful as input or output port for microprocessors functionally identical to abt373 3-state outputs for bus interfacing output sink capability of 64ma, source capability of 32ma guaranteed output skew guaranteed multiple output switching specifications output switching specified for both 50pf and 250pf loads guaranteed simultaneous switching, noise level and dynamic threshold performance guaranteed latchup protection high-impedance, glitch-free bus loading during entire power up and power down nondestructive, hot insertion capability general description the abt573 is an octal latch with buffered common latch enable (le) and buffered common output enable (oe ) inputs. this device is functionally identical to the abt373 but has broadside pinouts. ordering information devices also available in tape and reel. specify by appending the suffix letter ??to the ordering number. pb-free package per jedec j-std-020b. note: 1. device available in tape and reel only. order number package number package description 74abt573csc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74abt573cscx_nl (1) m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74abt573csj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74abt573cmsa msa20 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide 74abt573cmtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74abt573cmtcx_nl (1) mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 2 connection diagram pin descriptions functional description the abt573 contains eight d-type latches with 3-state output buffers. when the latch enable (le) input is high, data on the d n inputs enters the latches. in this condition the latches are transparent, i.e., a latch output will change state each time its d input changes. when le is low the latches store the information that was present on the d inputs a setup time preceding the high-to-low transition of le. the 3-state buffers are controlled by the output enable (oe ) input. when oe is low, the buffers are in the bi-state mode. when oe is high the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. function table h = high voltage level l = low voltage level x = immaterial o 0 = value stored from previous clock cycle logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. pin names descriptions d 0 ? 7 data inputs le latch enable input (active high) oe 3-state output enable input (active low) o 0 ? 7 3-state latch outputs inputs outputs oe le d o lhh h lhl l llx o 0 hxx z
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 3 absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. note: 2. either voltage limit or current limit is sufficient to protect inputs. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating t stg storage temperature ?5? to +150? t a ambient temperature under bias ?5? to +125? t j j unction temperature under bias ?5? to +150? v cc v cc pin potential to ground pin ?.5v to +7.0v v in input voltage (2) ?.5v to +7.0v i in input current (2) ?0ma to +5.0ma v o v oltage applied to any output disabled or power-off state high state ?.5v to 5.5v ?.5v to v cc current applied to output in low state (max.) twice the rated i ol (ma) dc latchup source current ?00ma over voltage latchup (i/o) 10v symbol parameter rating t a f ree air ambient temperature ?0? to +85? v cc supply voltage +4.5v to +5.5v ? v / ? t minimum input edge rate data input enable input 50mv/ns 20mv/ns
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 4 dc electrical characteristics notes: 3. for 8-bits toggling, i ccd < 0.8ma/mhz. 4. guaranteed but not tested. symbol parameter v cc conditions min. typ. max. units v ih input high voltage recognized high signal 2.0 v v il input low voltage recognized low signal 0.8 v v cd input clamp diode voltage min. i in = ?8ma ?.2 v v oh output high voltage min. i oh = ?ma 2.5 v i oh = ?2ma 2.0 v ol output low voltage min. i ol = 64ma 0.55 v i ih input high current max. v in = 2.7v (4) 1a v in = v cc 1 i bvi input high current breakdown t est max. v in = 7.0v 7 a i il input low current max. v in = 0.5v (4) ? ? v in = 0.0v ? v id input leakage test 0.0 i id = 1.9 ?, all other pins grounded 4.75 v i ozh output leakage current 0?.5v v out = 2.7v, oe = 2.0v 10 ? i ozl output leakage current 0?.5v v out = 0.5v, oe = 2.0v ?0 ? i os output short-circuit current max. v out = 0.0v ?00 ?75 ma i cex output high leakage current max. v out = v cc 50 ? i zz bus drainage test 0.0 v out = 5.5v, all others gnd 100 ? i cch po w er supply current max. all outputs high 50 ? i ccl po w er supply current max. all outputs low 30 ma i ccz po w er supply current max. oe = v cc , all others at v cc or gnd 50 ? i cct additional i cc /input outputs enabled max. v i = v cc ?2.1v 2.5 ma outputs 3-state enable input v i = v cc ?2.1v 2.5 ma outputs 3-state data input v i = v cc ?2.1v, all others at v cc or gnd 2.5 ma i ccd dynamic i cc no load (4) max. outputs open, oe = gnd, le = v cc (3) , one-bit toggling, 50% duty cycle 0.12 ma/ mhz
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 5 dc electrical characteristics soic package. notes: 5. max number of outputs defined as (n). n ?1 data inputs are driven 0v to 3v. one output at low. guaranteed, but not tested. 6. max number of outputs defined as (n). n ?1 data inputs are driven 0v to 3v. one output high. guaranteed, but not tested. 7. max number of data inputs (n) switching. n ?1 inputs switching 0v to 3v. input-under-test switching: 3v to threshold (v ild ), 0v to threshold (v ihd ). guaranteed, but not tested. ac electrical characteristics soic and ssop package. symbol parameter v cc conditions c l = 50pf, r l = 500 ? min. typ. max. units v olp quiet output maximum dynamic v ol 5.0 t a = 25? (5) 0.7 1.0 v v olv quiet output minimum dynamic v ol 5.0 t a = 25? (5) ?.5 ?.2 v v ohv minimum high level dynamic output voltage 5.0 t a = 25? (6) 2.5 3.0 v v ihd minimum high level dynamic input v oltage 5.0 t a = 25? (7) 2.2 1.8 v v ild maximum low level dynamic input voltage 5.0 t a = 25? (7) 1.0 0.7 v symbol parameter t a = +25?, v cc = +5.0v, c l = 50pf t a = ?0? to +85?, v cc = 4.5v to 5.5v, c l = 50pf units min. typ. max. min. max. t plh propagation delay, d n to o n 1.9 2.7 4.5 1.9 4.5 ns t phl 1.9 2.8 4.5 1.9 4.5 t plh propagation delay, le to o n 2.0 3.1 5.0 2.0 5.0 ns t phl 2.0 3.0 5.0 2.0 5.0 t pzh output enable time 1.5 3.1 5.3 1.5 5.3 ns t pzl 1.5 3.1 5.3 1.5 5.3 t phz output disable time 2.0 3.6 5.4 2.0 5.4 ns t plz 2.0 3.4 5.4 2.0 5.4
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 6 ac operating requirements soic and ssop package. extended ac electrical characteristics soic package. notes: 8. this specification is guaranteed but not tested. the limits apply to propagation delays for all paths described switching in phase (i.e., all low-to-high, high-to-low, etc.). 9. this specification is guaranteed but not tested. the limits represent propagation delay with 250pf load capacitors in place of the 50pf load capacitors in the standard ac load. this specification pertains to single output switching only. 10. this specification is guaranteed but not tested. the limits represent propagation delays for all paths described switching in phase (i.e., all low-to-high, high-to-low, etc.) with 250 pf load capacitors in place of the 50pf load capacitors in the standard ac load. 11. the 3-state delay times are dominated by the rc network (500 ? , 250pf) on the output and has been excluded from the datasheet. symbol parameter t a = +25?, v cc = +5.0v, c l = 50pf t a = ?0? to +85?, v cc = 4.5v to 5.5v, c l = 50pf units min. typ. max. min. max. f t oggle max toggle frequency 100 mhz t s (h) set time, high or low d n to le 1.5 1.5 ns t s (l) 1.5 1.5 t h (h) hold time, high or low d n to le 1.0 1.0 ns t h (l) 1.0 1.0 t w (h) pulse width, le high 3.0 3.0 ns symbol parameter t a = ?0? to +85?, v cc = 4.5v to 5.5v, c l = 50pf, 8 outputs switching (8) t a = ?0? to +85?, v cc = 4.5v to 5.5v, c l = 250pf (9) t a = ?0? to +85?, v cc = 4.5v to 5.5v, c l = 250pf, 8 outputs switching (10) units min. max. min. max. min. max. t plh propagation delay, d n to o n 1.5 5.2 2.0 6.8 2.0 9.0 ns t phl 1.5 5.2 2.0 6.8 2.0 9.0 t plh propagation delay, le to o n 1.5 5.5 2.0 7.5 2.0 9.5 ns t phl 1.5 5.5 2.0 7.5 2.0 9.5 t pzh output enable time 1.5 6.2 2.0 8.0 2.0 10.5 ns t pzl 1.5 6.2 2.0 8.0 2.0 10.5 t phz output disable time 1.0 5.5 (11) (11) ns t plz 1.0 5.5
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 7 skew (12) soic package. notes: 12. this specification is guaranteed but not tested. the limits apply to propagation delays for all paths described switching in phase (i.e., all low-to-high, high-to-low, etc.) 13. this specification is guaranteed but not tested. the limits represent propagation delays with 250pf load capacitors in place of the 50pf load capacitors in the standard ac load. 14. skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. the specification applies to any outputs switching high-to-low (t oshl ), low-to-high (t oslh ), or any combination switching low-to-high and/or high-to-low (t ost ). this specification is guaranteed but not tested. 15. this describes the difference between the delay of the low-to-high and the high-to-low transition on the same pin. it is measured across all the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. this specification is guaranteed but not tested. 16. propagation delay variation for a given set of conditions (i.e., temperature and v cc ) from device to device. this specification is guaranteed but not tested. capacitance note: 17. c out is measured at frequency f = 1mhz per mil-std-883b, method 3012. symbol parameter t a = ?0? to +85?, v cc = 4.5v to 5.5v, c l = 50pf, 8 outputs switching (12) t a = ?0? to +85?, v cc = 4.5v to 5.5v, c l = 250pf, 8 outputs switching (13) units max. max. t oshl (14) pin to pin skew, hl transitions 1.0 1.5 ns t oslh (14) pin to pin skew, lh transitions 1.0 1.5 ns t ps (15) duty cycle, lh?l skew 1.4 3.5 ns t ost (14) pin to pin skew, lh/hl transitions 1.5 3.9 ns t pv (16) device to device skew lh/hl tr ansitions 2.0 4.0 ns symbol parameter conditions (t a = 25?) typ. units c in input capacitance v cc = 0v 5 pf c out (17) output capacitance v cc = 5.0v 9 pf
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 8 ac loading *includes jig and probe capacitance figure 1. test load figure 2. test input signal levels figure 3. test input signal requirements ac wa veforms figure 4. propagation delay waveforms for inverting and non-inverting functions figure 5. propagation delay, pulse width waveforms figure 6. 3-state output high and low enable and disable times figure 7. setup time, hold time and recovery time waveforms amplitude rep. rate t w t r t f 3.0v 1mhz 500ns 2.5ns 2.5ns
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 9 physical dimensions dimensions are in inches (millimeters) unless otherwise noted. figure 8. 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide pa ck ag e number m20b
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 10 physical dimensions (continued) dimensions are in millimeters unless otherwise noted. figure 9. 20-lead small outline package (sop), eiaj type ii, 5.3mm wide pa ck ag e number m20d
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 11 physical dimensions (continued) dimensions are in millimeters unless otherwise noted. figure 10. 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide pa ck ag e number msa20
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 12 physical dimensions (continued) dimensions are in millimeters unless otherwise noted. figure 11. 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa ck ag e number mtc20
74abt573 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74abt573 rev. 1.4 13 tradem a rks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intend ed to be an exhaustive list of all such trademarks. acex across the board. around the world. activearray bottomless build it now coolfet crossvolt ctl current transfer logic dome e 2 cmos ecospark ensigna fact quiet series fact fast fastr fps frfet globaloptoisolator gto hisec i-lo implieddisconnect intellimax isoplanar microcoupler micropak microwire msx msxpro ocx ocxpro optologic optoplanar pacman pop power220 power247 poweredge powersaver powertrench programmable active droop qfet qs qt optoelectronics quiet series rapidconfigure rapidconnect scalarpump smart start spm stealth superfet supersot -3 supersot -6 supersot -8 syncfet tcm the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinywire trutranslation p serdes uhc unifet vcx wire disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild? worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ich, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. re v. i24

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